Digital Quantum Simulation

Co-designed Quantum Processors and Algorithms

Simulating fermionic models in quantum computers is a challenging task. Guarantying the corresponding Fermi statistics requires non-local encodings, imposing overheads in circuit depths and qubit numbers. Since these resources are limited in near-term devices, finding more efficient approaches to simulate fermionic models is an important task, considering the relevance of this problem to many fields of physics. In this direction, we have developed a fermionic quantum processor to perform hardware-efficient digital simulations of fermionic models using fermionic atoms in tweezer arrays. We proposed how to implement digital tunneling gates that guarantee Fermi statistics at the hardware level, allowing for efficient circuit decompositions of arbitrary fermionic interactions, and designed protocols for fermionic error correction. Additionally, we have developed state-preparation protocols for condensed-matter models tailored to the resources available in optical lattice setups.

In the lattice gauge theory framework, space-time is discretized in a way that allows to encode these theories into classical computers and perform numerical simulations, while still retaining the relevant symmetry properties. This is however not true in general for a quantum computer. While finite gauge fields can be encoded naturally into qubit or qudit devices, this cannot be done exactly for the infinite-dimensional continuous gauge fields relevant for the Standard Model of Particle Physics, which should be first truncated in a way that allows to extract the continuous limit of the theory. In this work, we used quantum groups to approximate them in a systematic manner. A key property of this approach is that it retains unitarity, allowing us to efficiently construct exact quantum circuits to simulate their dynamics, as well as to built tensor-network ansatzes to benchmark them. At the moment, we are also developing more efficient encodings for fermionic models,  with the goal of considerably reducing circuit-depth overheads in qubit devices.